1. Field of the Invention
The present invention relates generally to selective modification of the surface of a workpiece. More particularly, the present invention relates to selectively modifying the workpiece surface to allow selective deposition on the workpiece, such as selective deposition on a semiconductor substrate during integrated circuit fabrication.
2. Description of the Related Art
Many steps are typically performed to manufacture multi-level interconnects for integrated circuits (IC). Such steps include depositing conducting and insulating materials on a workpiece, such as a semiconductor substrate or wafer, followed by full or partial removal of these materials using photolithography to pattern photoresist to selectively remove material by selective exposure to etchant, such as during damascene processing, to form a desired pattern of recessed features such as vias, contact holes, lines, trenches and channels. These features may be referred to generally as recesses or cavities, and the overlying surfaces in which the features are formed may be referred to as field areas or the top surface of the workpiece. Typically, the field areas are planar. The recesses typically come in a wide variety of dimensions and shapes and are filled with a highly conductive material using electro- or electroless plating or other methods of material deposition. Common filling techniques deposit material both in the recesses and on the field areas. Consequently, additional processing steps such as etching and/or chemical mechanical polishing (CMP) are typically performed to remove the excess material deposited on field areas. A low resistance interconnection structure is formed between the various sections of the IC after completing these deposition and removal steps multiple times.
Copper (Cu) and copper alloys are typically used for interconnections in ICs because of their low electrical resistivity and high resistance to electromigration. Electrodeposition is a common method for depositing copper into recesses on a workpiece surface.
A conventional electrodeposition method and apparatus are described in FIGS. 1A and 1B. FIG. 1A illustrates a cross-sectional view of a workpiece 10 having an insulator forming its top section. Using conventional deposition and etching techniques, features 18a, 18b such as a dense array of small vias 18a or trenches 18b are formed in the workpiece. Typically, the widths of the vias 18a may be sub-micron. The vias 18a may be narrow and deep; in other words, they can have high aspect ratios (i.e., their depth to width ratio is large). A dual-damascene structure (not shown), on the other hand, has a wide trench and a small via on the bottom. The wide trench has a small aspect ratio.
FIG. 1B illustrates a conventional method for filling the recesses of FIG. 1A with copper. The workpiece 10 and the insulator have deposited thereon a barrier or adhesion layer and a seed layer' overlying the barrier or adhesion layer. For ease of illustration, the barrier and seed layer are referred to together by the reference numeral 12.
With reference to FIG. 1B, after depositing the seed layer 12, a conductive material 14, e.g., copper, is electrodeposited on the seed layer 6 from a plating bath. During this step, electrical contact is made to the seed layer and/or the barrier layer 12 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the conductive material 14 is electrodeposited over the workpiece surface using the plating solution. The seed layer 12 is shown as an integral part of the deposited layer of conductive material 14 in FIG. 1B. By using additives, such as chloride ions, suppressors/inhibitors, and accelerators, it is possible to obtain bottom-up growth of conductive material (such as copper) in the recesses.
As shown in FIG. 1B, the deposited copper 14 completely fills the vias 18a and is generally conformal in the large trench 18b. Copper does not completely fill the trench 18b, however, because the additives are not operative in large features. For example, it is believed that the bottom up deposition observed in vias and other features with large aspect ratios occurs because the suppressor/inhibitor molecules attach themselves to the top portion of the feature openings to suppress the material growth thereabouts. These molecules cannot effectively diffuse through the narrow openings to the bottom surface of high aspect ratio features such as the vias 18a of FIG. 1. Preferential adsorption of the accelerator on the bottom surface of the vias 18a, moreover, results in faster growth in that region, resulting in bottom-up growth and the copper deposit profile shown in FIG. 1B. Consequently, as can be seen in FIG. 1B, the relatively large aspect ratio features 18a are overfilled, while relatively large aspect ratio features 18b are filled more conformally. It will be appreciated that, without the appropriate additives, copper can grow on the vertical walls as well as the bottom surface of the high aspect ratio features at the same rate, thereby causing defects such as seams and voids, as is well known in the industry.
In the next step of interconnect formation, excess deposited material 14 is removed from the field areas of the workpiece 10, leaving conductive material 14 in trenches, vias and other recesses in the workpiece. This step eliminates electrical contacts between interconnects or other features formed by the conductive material 14. As known in the art, a common technique for selective material removal from the top of a workpiece is Chemical Mechanical Planarization (CMP). After the CMP step, the material 14 is completely removed from field areas 14, as shown in FIG. 1C.
CMP technology is well accepted in the integrated circuit fabrication industry and has became a standard part of manufacturing processes. However, various problems may limit the use of CMP in the fabrication of future generations of integrated circuits. These problems include, for example, dishing and erosion (excessive removal of conducting or dielectric material), high process cost, defects, and limited applicability for low-k materials.
To reduce or eliminate the problems associated with CMP, several methods have been developed for selective material deposition in only recessed areas of a workpiece.
A new class of plating techniques, called Electrochemical Mechanical Deposition (ECMD), has been developed to deposit material on workpieces with cavities. U.S. Pat. No. 6,176,992, entitled “Method and Apparatus for Electrochemical Mechanical Deposition”, discloses a technique that achieves deposition of the conductive material into the cavities on a workpiece surface, while minimizing deposition on field regions. This ECMD process results in planar material deposition; but simultaneous polishing and material deposition is prone to critical defect formation.
U.S. Pat. Nos. 7,051,934, 6,974,775, 6,787,460, and 6,410,418 describe various other methods for selective plating or deposition. These methods, however, are faced with various problems that limit their practical applicability.
Accordingly, a need exists for methods and systems for controlling deposition onto desired parts of a workpiece.